3D Chips Running Too Hot
Master 3D-IC thermo-mechanical stress: early thermal modeling, foundry stress-aware PDKs and EDA-integrated simulation flows for reliable multi-chip design
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To manage thermal and mechanical stresses in multi-chip modules, it is necessary to have a detailed understanding of the device’s usage methods and locations, packaging methods, and any issues that stresses might cause at any point during the expected lifespan.
This includes various factors ranging from workload-related thermal gradients to mechanical and electrical stresses, which become more pronounced with the emergence of aging effects (such as electromigration and dielectric breakdown). The most advanced GPUs currently operate at around 500 watts, but with increasing transistor utilization in AI applications, this value could rise to 1000 watts per square centimeter, making heat dissipation particularly challenging. In turn, due to thermal mismatches between materials, this can lead to mechanical deformations—warping, cracking, and delamination.
In the past, thermal modeling and management were typically separate tasks, related to circuit design and computational architecture, but in multi-chip modules, they need to be addressed together.
John Ferguson, Senior Director of Product Management for Siemens EDA Calibre 3D IC Solutions, said: “The main concern everyone has is reliability issues. This primarily stems from the manufacturing process, where, during chip assembly, heating, and cooling, various materials expand and contract at different rates. This can lead to delamination, which in turn causes chip separation. Connections may fail as a result, which is a very serious problem.”
