Big-Chip Packaging: A Tripartite World
AI-chip packaging race: TSMC, Intel, Samsung vie for $80B 2030 market—capacity, cost, security decide winners.
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In the wave of rapid development of AI chips, GPUs, AI ASICs, and other high-performance computing (HPC) cores, as well as HBM (high-bandwidth memory), are becoming the mainstay of high-end products adopting 2.5D/3D packaging technology. Advanced packaging platforms are crucial for improving device performance and bandwidth, and their importance has made them the hottest topic in the semiconductor field, with popularity even surpassing that of previous cutting-edge process nodes.
Recently, news that Intel’s advanced packaging technology EMIB is being evaluated by tech giants Apple and Qualcomm has attracted widespread attention: Apple, in its relevant job postings, is seeking DRAM packaging engineers familiar with technologies such as CoWoS, EMIB, SoIC, and PoP; Qualcomm is also recruiting a data centre product management director, requiring familiarity with Intel’s EMIB technology. Although these moves do not yet mean that the two major chip design giants have officially switched, they clearly reveal that the world’s top self-developed chip companies are actively evaluating Intel as a potential alternative to TSMC.
In the field of advanced packaging for AI chips, TSMC, Intel, and Samsung have formed a “tripod” pattern. Due to their different positions, these three companies also play different packaging roles in the industry chain. According to Yole Group’s analysis, in the short term, advanced packaging revenue in the second quarter of 2025 will exceed $12 billion. Driven by strong demand for artificial intelligence and high-performance computing, the market performance in the second half of the year is expected to be even stronger. In the long term, the advanced packaging market size in 2024 is approximately $45 billion, expected to grow at a robust compound annual growth rate of 9.4%, reaching about $80 billion by 2030.
