For sixty years, the semiconductor industry’s most fundamental measuring stick has been the nanometer. From 90 nm all the way down to 2 nm, the continual shrinking of transistors has directly determined the life or death of chips. In the AI era, however, the industry has been handed a second critical measuring stick—the reticle multiple.
On August 11, at the 2026 OCP APAC Summit, TSMC’s Vice President of Advanced Packaging Technology and Service, Ho Chun, revealed that TSMC has successfully mass-produced CoWoS packages at 5.5× reticle size, with yields stably maintained above 98%. Looking ahead, the company plans to push toward 14× reticle size and even higher multiples.
In fact, TSMC’s technology roadmap released in April of this year already laid out a clear timeline for this evolution: 14× reticle-size CoWoS is scheduled for mass production in 2028 and will be able to integrate approximately 10 large compute dies and 20 HBM stacks. By 2029, package size is expected to break through the 14× reticle limit.
This is a rather astonishing figure. TSMC has previously disclosed that a standard reticle size corresponds to an area of roughly 830 mm². A simple area conversion would put 14× reticle size at more than 11,000 mm². Of course, the so-called “14× reticle” does not mean fabricating a single photomask that is literally 14 times larger in area. Rather, it describes the overall advanced-packaging interposer, RDL, and chiplet integration area that now spans more than a dozen individual lithography exposure fields.
From the original 1× and 2×, through 3× and 5.5×, and now racing toward 14×, an increasingly clear trend has emerged: advanced packaging is rapidly “inflating.”
